Weekly Status Report

FPGA Gate Count Estimate

Peter Deutsch

• A rough estimate has been made for the number of logic modules required to compile TensorFlow model onto an FPGA.
• Lower bound is acceptable but difficult to achieve.
• Upper bound is way to high.

Research

Everyone

• Reading into LeFlow paper: compiling TensorFlow (Python) model into synthesizable Verilog.
  • Not very efficient.
  • General consensus is that we don’t pursue this option unless our ML model is extremely good but difficult to implement as hardware.
• Optimization of Convolutional Neural Nets (CNN) on FPGA.
  • Unique architecture and timing and achieves fastest FPGA performance for a neural net ~60GFLOPs for 100MHz clock.
  • A bit too ambitious (for now).

Risk Management

Everyone

Risk	Likelihood	Impact	Risk
FPGA logic capacity is not enough to implement our solution.	0.5	1	0.5
Accidents that damage to drone and FPGA that leads to extra budget that we may not have.	0.7	0.7	0.49
Forced to buy cheaper components which leads to lower performance.	0.8	0.5	0.4
Deliveries is not meeting client’s expectations	0.2	0.8	0.4
Knowledge and skill (Machine Learning & Computer vision) required for project is not sufficient.	0.5	0.8	0.4
Our scrum method is not efficient	0.5	0.7	0.35
Scope of the project is underestimated which leads to burn outs	0.5	0.7	0.35
Not have enough money.	0.5	0.7	0.35
Not enough time commitment from team member due to other courses.	0.5	0.6	0.3
Team is indecisive which leads to delay - management is not good enough to make a timely decision.	0.4	0.7	0.28

Project Proposal

Everyone

• See Trello for division of labor
• Draft before next Tuesday (first review and revision with the client).
• Second draft before next Thursday (second review and revision with instructors).

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